This invention relates to Micro-Electro-Mechanical-Systems (MEMS) and more particularly to a wafer level MEMS packaging technique which prevents processing related micro-contamination.
The manufacturing of Micro-Electro-Mechanical-Systems (MEMS) such as micro-gyroscopes, micro-accelerometers, resonant accelerometers, micro-mirrors, micro-motors, micro-actuators and other such micro-devices, for automotive, photonics, information technology and bio-mechanical markets, integrating at least one moving and/or particular component causes a very serious challenge for packaging because:
Some MEMS-based devices require the encapsulation to be done before dicing, as to be protected against micro-contamination from particles and dicing slurry while being processed like a standard semiconductor chip, without the need for dedicated equipment or processes for dicing, mounting and molding procedures inside the cleanrooms.
Changes in atmospheric conditions can change the capacitance readout of micro-gyroscopes and micro-accelerometers without any changes in acceleration and because an increased relative humidity can increase stiction of their moving parts, it is necessary to encapsulate their moving and/or particular components in vacuum or in a controlled atmosphere.
Most MEMS-based resonant accelerometers, most MEMS-based RF switching devices and other such MEMS devices have very serious Q-factor degradation when exposed to an ambient pressure exceeding 1 Pa. Their moving MEMS components require a vacuum packaging to a residual pressure of less then 1 Pa as to ensure a reliable service during its complete projected life.
To ensure these functions, the moving and/or particular component should be enclosed in a sealed micro-cavity under a vacuum of less then 1 Pa.
A first example of protective packaging is provided in FIG. 1 taken from the following cited Prior Art reference:
U.S. Pat. No. 5,589,082 titled xe2x80x98Microelectromechanical signal processor to fabricationxe2x80x99 (The Regents of the University of California).
The micro-cavity described in U.S. Pat. No. 5,589,082 is used to protect a micro-mechanical resonator and is formed using a vacuum sealed silicon nitride micro-shell fabricated by:
Properly micromachining the micro-mechanical resonator to a certain fabrication step;
Depositing a 7.0 xcexcm thick phosphosilicate (PSG) layer over the micromachined micro-mechanical resonator;
Patterning the 7.0 xcexcm thick PSG layer into an isolated island covering the moving and/or particular component of the micromachined micro-mechanical resonator and defining the shape of the micro-shell;
Depositing an extra 1.0 xcexcm thick PSG layer;
Patterning the lateral etch-channels at the periphery of the isolated island of FIG. 1;
Depositing an extra 1.0 xcexcm thick LPCVD low-stress silicon nitride;
Patterning the lateral etch holes in the silicon nitride located at the periphery of the isolated island;
Release of the micro-mechanical resonator using concentrated HF penetration through the lateral etch holes formed at the periphery of the isolated island of all sacrificial material located under and over (7.0 xcexcm thick PSG layer) the moving and/or particular component of the micromachined micro-mechanical resonator, leaving the formed 1.0 xcexcm thick LPCVD low-stress silicon nitride micro-shell intact;
Sealing of the lateral etch holes formed at the periphery of the formed micro-shell using a 2.0 xcexcm thick layer of silicon nitride deposited over the suspended 1.0 xcexcm thick LPCVD low-stress silicon nitride micro-shell, as to form a 3.0 xcexcm thick LPCVD low-stress silicon nitride micro-shell.
As indicated in the patent at column 11, lines 7-12, the release of the micro-mechanical resonator using concentrated HF through the lateral etch holes formed at the periphery of the silicon micro-shell limits the size of the micro-device to about 500 xcexcmxc3x97500 xcexcm due to:
Incomplete sacrificial material removal away from the periphery of the micro-shell;
Collapse of the 3.0 xcexcm thick LPCVD low-stress silicon nitride micro-shell upon exposure to atmospheric pressure.
A second example of protective packaging is provided in FIG. 2 taken from the following cited Prior Art reference:
U.S. Pat. No. 5,668,033 titled xe2x80x98Method for manufacturing a semiconductor acceleration sensor devicexe2x80x99.
The packaging technique of U.S. Pat. No. 5,668,033, used to fabricate the packaging structure covering the acceleration sensor uses gold-silicon (case where a silicon-on-insulator substrate is used) or gold-polysilicon eutectic bonding technique.
This technique requires the bonding of two substrates.
A third example of protective packaging is provided in FIG. 3 taken from the following cited Prior Art reference:
U.S. Pat. No. 5,783,749 titled xe2x80x98Vibrating disk type micro-gyroscopexe2x80x99 (Electronics and telecommunications research Institute).
The packaging technique of U.S. Pat. No. 5,783,749, used to fabricate the vacuum sealed packaging structure covering the gyroscope as to maintain a 1 mTorr pressure to enhance its sensitivity and to minimise air damping, uses an unknown bonding technique.
This technique also requires the bonding of two elements, i.e. of a sealed structure and of a substrate, as indicated in column 3D, lines 25-31.
A fourth example of protective packaging is provided in FIG. 4 taken from the following cited Prior Art reference:
U.S. Pat. No. 5,952,572 titled xe2x80x98Angular rate sensor and acceleration sensorxe2x80x99 (Matsushita Electric Industrial Co., Ltd.).
The three substrates composing the angular rate sensor described in U.S. Pat. No. 5,952,572 are bonded together as a sandwich structure using anodic bonding, as mentioned in column 7, lines 36-41. This anodic bonding requires the silicon and glass substrates to be heated at 300-400xc2x0 C. in vacuum while a negative voltage of about 1000V in terms of reference potential of the silicon substrate is applied to the glass substrates. As mentioned in column 7, lines 55-58, a Zrxe2x80x94Vxe2x80x94Fe/Ti non-volatile getter material is also integrated in the sealed cavity as to maintain the vacuum quality.
This technique also requires the bonding of two substrates.
A fifth example of such protective packaging is provided in FIG. 5 taken from the following cited Prior Art reference which also review the Prior Art in microsensor""s packaging, as of April of 1997:
U.S. Pat. No. 6,140,144 titled xe2x80x98Method for packaging microsensorsxe2x80x99 (Integrating Sensing Systems, Inc.).
The two substrates composing the microsensors described in U.S. Pat. No. 6,140,144 are bonded together via flip chip bonding using an underfill material as to maintain a controlled pressure/controlled environment around the sensing element, as mentioned in column 3, lines 48-50.
This technique also requires the bonding of two substrates.
A sixth example of such protective packaging is provided in FIG. 6 taken from the following cited Prior Art reference:
U.S. Pat. No. 6,232,150 titled xe2x80x98Process for making microstructures and microstructures made therebyxe2x80x99 (The Regents of the University of Michigan).
The two substrates composing the microstructures described in U.S. Pat. No. 6,232,150 are bonded together using a localised micro-heater flip chip bonding using a bonding material and a metal-based localised resistive micro-heater capable of locally heating the bonding material as to provoke the bonding of the two substrates, as mentioned in column 4, lines 25-35.
This technique also requires the bonding of two substrates.
A seventh example of such protective packaging is provided in FIG. 7 taken from the following cited Prior Art reference;
U.S. Pat. No. 6,265,246 titled xe2x80x98Microcap wafer-level packagexe2x80x99 (Agilent Technologies, Inc.).
The base wafer integrating a micro-device described in U.S. Pat. No. 6,265,246 is bonded to a matching cap wafer using cold welding of the bonding pad gaskets of the cap wafer to the periphery of the bonding pads of the base wafer integrating the micro-device. The arrangement assures an hermetic seal of the wafer-level package and electrical connections to the micro-device without passing through a seal.
This technique also requires the bonding of two substrates.
An eighth example of such protective packaging is provided in FIG. 8 taken from the following cited Prior Art reference:
U.S. Pat. No. 6,297,072 titled xe2x80x98Formation of a microstructure having an internal cavityxe2x80x99 (Interuniversitair Micro-Electronika Centrum, IMEC, VZW).
A first chip located on first substrate covered with antimony-copper or antimony-nickel/gold metallization seed layer forming a stable intermetallic compound with a selected solder is bonded to a second chip located on a second substrate also covered with antimony-copper or antimony-nickel/gold metallization seed layer via an antimony-lead, an antimony-lead-silver, an indium, a gold-antimony, an antimony-silver, an antimony-silver-copper or an antimony-bismuth electroplated solder ring capable of being reflowed at 200-350xc2x0 C. as to create an enclosed vacuum or controlled ambient cavity.
This technique also requires the bonding of two substrates.
An ninth example of such protective packaging is provided in FIG. 9 taken from the following cited Prior Art reference:
U.S. Pat. No. 6,335,224 titled xe2x80x98Protection of microelectronic devices during packagingxe2x80x99 (Sandia Corporation).
A released MEMS element is protected by a water-insoluble vacuum vapor deposited conformal and dry-etchable temporary protective coating such as parylene during dicing allowing its protection against micro-contamination. This protective coating is later removed using an oxygen plasma when the diced MEMS or IMEMS device substrate is bonded to the package and when the bond pads of the MEMS device are electrically connected to the external electrical leads with bond wires. Following the removal of the protective coating, a cover lid including an optional optical window is bonded to the package protecting the released MEMS element.
This technique requires a temporary protective coating to be removed using an oxygen plasma during die packaging, just prior to cover lid bonding.
Robert Bosch GmbH is probably one of the leading groups in surface micromachining. The Prior Art description will try to cover the work performed by this group in the development of MEMS packaging:
FIG. 10 is taken from the following cited Prior Art reference:
U.S. Pat. No. 5,937,275 titled xe2x80x98Method of producing acceleration sensorsxe2x80x99 (2.10.1. Robert Bosch GmbH).
Referring to FIG. 10, this U.S. Pat. No. 5,937,275 claims in its claim 1: A method for producing sensors, especially acceleration sensors in which on a substrate (1) with a sacrificial layer (2), in an epitaxial application system, a silicon layer (4) is deposited that is deposited above the sacrificial layer (2) as a polysilicon layer (6), a first photoresist layer (not illustrated) being applied to the polysilicon layer (6) and being structured by optical methods as an etching mask, and structures (not illustrated) being introduced into the polysilicon layer (6) through the etching mask, which structures extend from the top side of the polysilicon layer (6) as far as the sacrificial layer (2), a sacrificial layer (2) being removed from beneath the structures (not illustrated), characterized in that the surface of the polysilicon layer (6) is post-machined in a smoothing process before the first photoresist layer (not illustrated) is applied. Amongst other things, the other claims cover: the use of a photoresist plasma etch-back planarization process for the polysilicon layer, a chemical-mechanical polishing process of the polysilicon layer, a polysilicon starter layer under the polysilicon layer, a polysilicon layer over the sacrificial layer simultaneously to an epitaxial growth over the regions where no sacrificial layer is provided.
This first patent does not yet describe the protective cavity that Robert Bosch GmbH uses around the moving and/or particular component of the MEMS device.
FIG. 11 shows an example of the surface micromachining performed at Robert Bosch GmbH, as reported on the Europractice web site:
http://www.europractice.bosch.com/en/download/customer_support. pdf
This FIG. 11 shows that a 380 xcexcm thick Cap wafer is used as to form a 75 xcexcm high protective cavity over the 10.3 xcexcm thick released polysilicon structures.
Some details of this surface micromachining process are also available in the following cited Prior Art reference:
M. Furtsch, M. Offenberg, H. Muenzel, J. R. Morante, xe2x80x98Comprehensive study of processing parameters influencing the stress and stress gradient of thick polysilicon layersxe2x80x99, SPIE Conference Proceedings xe2x80x98Micromachining and microfabrication process technology III, conference proceedingsxe2x80x99, SPIE Vol. 3223, pp. 130-141, Austin Tex., Sep. 29-30,1997.
This Furtsch""s Prior Art reference indicates that:
The starting material is a 150 mm (100) N-type 1-2 ohm cm resistivity silicon wafer;
The 2.5 xcexcm thick Pad oxide is thermally grown on the substrate;
The 0.45 xcexcm thick Surface polysilicon layer is deposited using a standard 630xc2x0 C. Low Pressure Chemical Vapor Deposition (LPCVD) process;
The 0.45 xcexcm thick Surface polysilicon layer is implanted with antimony and annealed at 1000xc2x0 C. in an oxygen ambient as to drive and activate the Sb dopant;
There is no indication on the fabrication technique of the 1-6 xcexcm thick Sacrificial oxide;
The 10.3 xcexcm thick Structural ISDP (In-Situ Doped Polysilicon) layer is deposited as a 11.8 xcexcm thick layer at a rate of 3.5 xcexcm/minute and at a temperature of 1180xc2x0 C. in a ASM Epsilon One Model-E2 single wafer epitaxy reactor using a standard trichlorosilane (SiHCl3), hydrogen (H2), and phosphine (PH3) process. The resulting 11.8 xcexcm thick Structural ISDP layer has an average surface roughness (Ra) of 260 nm, which is unacceptable for further processing. A chemical mechanical polishing (CMP) is then used to reduce the thickness of the Structural ISDP to 10.3 xcexcm and its surface roughness to about 5 xcexcm. The silicon single crystals growing epitaxially over the silicon substrate regions opened through the 2.5 xcexcm thick Pad oxide windows have a sheet resistance of 2 k/sq. The as-grown polycrystalline structure being higher then 100 M/sq., a 900xc2x0 C. POC13 doping is also performed, resulting in the growth of a 30 nm thick phosphorous glass (PSG) on top of the Structural ISDP. This thin grown PSG layer is removed using a standard HF etching solution. A protective oxide is grown at 900xc2x0 C. to prevent the out-diffusion of phosphorus during the following 7 hours duration 1000xc2x0 C. P-dopant drive-in in a nitrogen ambient. The protective oxide is then removed.
The Deep silicon etch patterns are generated using the technique described in the following Prior Art work:
M. Offenberg, F. Larmer, B, Elsner, H. Munrel and W. Rietlumuller, xe2x80x98Novel process for a monolithic integrated accelerometerxe2x80x99, Digest of technical papers: Transducers ""95xe2x80x94Eurosensors IX, Vol. 1, pp. 589-592, Stockholm, 1995.
The release of the Structural ISDP components is done using a HF vapor technique described in the following Prior Art work as to avoid sticking of the structures:
M. Offenberg, B, Elsner and P. Larmer, xe2x80x98HF vapor etching for sacrificial oxide removal in surface micromachiningxe2x80x99, Extended Abstracts Electrochem. Soc. Fall Meeting, Vol. 942, pp. 1056-1057, Miami Beach, 1994.
There are no further details about the 1.3 xcexcm thick Metal layer, about the 380 xcexcm thick Cap wafer nor about the 75 xcexcm Cavity.
Some details of this surface micromachining process are also available in the following cited Prior Art reference:
http://wvw.imec.be/SUMICAP/Welcome.html#who
Bosch currently uses glass frit to bond the Cap wafer to the substrate as to provide an hermetic seal. FIG. 12 shows an example of a Cap wafer glass frit bonded to the surface micromachined gyroscope produced at Robert Bosch GmbH.
The SUMICAP (SUrface MIcromachined enCAPsulation on wafer-level) project carried out by IMEC, Bosch and STS within the framework of the Information Societies Technology (IST) program of the European Commission (contract number IST-1999-10620) between January 2000 and December 2002 intends to develop a wafer-level encapsulation technique for MEMS using surface micromachined membranes over the device that needs to be encapsulated in a vacuum (below 100 Pa) or controlled atmosphere. This monolithic wafer-level packaging technique:
Should be capable of covering 1 mm by 1 mm MEMS devices having high aspect ratio trenches (1:5);
Should survive standard plastic molding;
Should use less chip area and material than the current capping process;
Should provide a 50% reduction of the total chip cost;
Should allow a vacuum in the cavity below 100 Pa.
The project managed by IMEC involves the following technology steps: Sacrificial oxide layer deposition, Membrane layer deposition, Sacrificial oxide etching using the standard STS equipment, Sealing layer deposition and Interconnections. The expected result is a wafer-level surface micromachined encapsulation in a plastic molding of an accelerometer demonstrator optimized using Bosch""s extensive simulations to decide on the required thickness and stress of membrane and sealing layer, the number of supports and the optimal sensor design.
The review of the cited Prior Art indicates that there is a need to improve the packaging techniques of MEMS devices as to ensure higher yields, higher performance and improved reliability.
Most of the cited Prior Art works describe the need for bonding multiple substrates as to get the required protective cavity around the moving and/or particular component of the MEMS device:
U.S. Pat. No. 5,668,033 titled xe2x80x98Method for manufacturing a semiconductor acceleration sensor devicexe2x80x99 (FIG. 2).
U.S. Pat. No. 5,783,749 titled xe2x80x98Vibrating disk type micro-gyroscopexe2x80x99 (FIG. 3).
U.S. Pat. No. 5,952,572 titled xe2x80x98Angular rate sensor and acceleration sensorxe2x80x99 (FIG. 4).
U.S. Pat. No. 6,140,144 titled xe2x80x98Method for packaging microsensorsxe2x80x99 (FIG. 5).
U.S. Pat. No. 6,232,150 titled xe2x80x98Process for making microstructures and microstructures made therebyxe2x80x99 (FIG. 6).
U.S. Pat. No. 6,265,246 titled xe2x80x98Microcap wafer-level packagexe2x80x99 (FIG. 7).
U.S. Pat. No. 6,297,072 titled xe2x80x98Formation of a microstructure having an internal cavityxe2x80x99 (FIG. 8).
http://www.europractice.bosch.com/en/download/customer_support.pdf (FIG. 11).
M. Furtsch, M. Offenberg, H. Muenzel, J. R. Morante, xe2x80x98Comprehensive study of processing parameters influencing the stress and stress gradient of thick polysilicon layersxe2x80x99, SPIE Conference Proceedings xe2x80x98Micromachining and microfabrication process technology III, conference proceedingsxe2x80x99, SPIE Vol. 3223, pp. 130-141, Austin Tex., Sep. 29-30, 1997 (FIG. 11).
The currently available technique of bonding multiple substrates as to get the protective cavities causes the previously mentioned cost, yield, performance and reliability limitations.
The following reference:
http://www.sensorsmag.com/articles/1298/sil1298/main.shtml was used to generate the following summary table of the main bonding options for these multiple substrates, which are: Anodic bonding, glass frit bonding and direct wafer bonding.
It is clear from the upper table that the direct wafer bonding (DWB) technique is not suitable because the bonding of the protective cavity is performed after the metallisation step and the required 1000xc2x0 C. is simply incompatible with it.
It is also clear that the glass frit bonding is also unsatisfactory for most applications because the poor 1300 Pa achievable vacuum way higher then the expected 1 Pa vacuum level degrades the Q-factor of most micro-gyros, of most micro-accelerometers, of most differential resonant accelerometers and of many other MEMS-based devices requiring better then 1 Pa vacuum.
The anodic bonding technique is then the most appropriate one. It relies on charge migration in order to bond the silicon wafer to a glass cover containing a high content of alkali metals, such as Pyrex borosilicate glass which contains about 3.5% of sodium oxide (Na2O). The positive ions (Na+) of the glass are attracted by a highly negative potential applied to the glass, where they are neutralized. Such a Na+ ions removal permits the formation of a space charge at the glass-silicon interface, which creates a strong electrostatic attraction between the silicon wafer and the glass cover that holds both pieces firmly in place. The bond is performed at temperatures of up to 500xc2x0 C., which increases the mobility of the positive ions (Na+). Furthermore, driven by the existing electric field, oxygen from the glass is transported to the glass-silicon interface where it combines with silicon to form SiO2, which creates a permanent bond. This technique has been reported as producing uniform bonds; however, the presence of charge carriers makes this bond generally not compatible with active devices.
With an increased demand for lower cost CMOS integrated MEMS devices in cost-sensitive markets such as automotive, there is a clear need to avoid the use of anodic bonding or other multiple substrates bonding techniques; a low cost, simple, CMOS compatible cavity formation technique is required.
With an increased sophistication of the MEMS devices, from simple industrial pressure sensors to more complex automotive/aerospace micro-gyroscopes or photonics"" micro-mirrors, there is a serious need for higher yields and higher performance packaging capable of ensuring a 1 Pa vacuum in the surrounding of the moving and/or particular component of these higher performance and improved reliability.
The described IMEC-Bosch-STS SUMICAP project on-going within the IST program of the European Commission until December 2002 and intended to develop a wafer-level encapsulation technique for MEMS is a clear indication of the major technological need for the packaging of large size (more then 1 mm ) MEMS devices in standard plastic molding using surface micromachined membranes over MEMS devices that need to be encapsulated to below 100 Pa at a 50% reduced total chip cost.
The Sacrificial oxide layer deposition by Bosch, the Membrane layer deposition by Bosch, the Sacrificial oxide etching by STS equipment, the Sealing layer deposition by Bosch and the Interconnections by Bosch will probably soon result in the demonstration of the 100 Pa vacuum-sealed wafer-level surface micromachined encapsulation in a plastic molding of an accelerometer demonstrator optimized using Bosch""s extensive simulations. This 100 Pa performance goal will still be restrictive for the high performance (high Q-factor) micro-gyros, micro-accelerometers, differential resonant accelerormeters and other MEMS-based devices requiring a residual vacuum level better then 1 Pa.
In accordance with a first aspect of the present invention there is provided a process for fabricating an integrated, wafer-level protective cap on a micro-electronic device comprising: depositing first and second layers of sacrificial material during a fabrication stage of the device, the first and second layers of sacrificial material being selectively patterned; depositing and patterning an encapsulation structure over the second layer of sacrificial material; removing the patterned sacrificial material through the encapsulation structure by a vapor etch to form the micro-electronic device; and depositing a sealing layer over the encapsulation structure.
In accordance with a second aspect of the present invention there is provided a process for fabricating an integrated wafer-level protective cap for a micro-Electro-Mechanical-System (MEMS) device comprising: depositing and patterning a pad oxide layer on a silicon substrate; depositing and patterning a polysilicon layer on the pad oxide layer and silicon substrates; depositing and patterning a first layer of a sacrificial material; depositing and patterning structured In-Situ-Doped-Polysilicon (ISDP) on the first layer of sacrificial materials; patterning and deep etching the ISDP; depositing and patterning a second layer of sacrificial material; depositing an encapsulation structure over patterned second layer of sacrificial material; patterning the encapsulation structure; selectively removing the first and second layers of sacrificial material to create the MEMS; and depositing, under vacuum, a sealing layer over the encapsulated structure.
There is also provided an MEMS fabricated in accordance with the above methods.
The present application provides a competitive, simple, single-substrate, wafer-level packaging technique capable of creating the vacuum-sealed protective cavity around the moving and/or particular component of these higher performance and improved long-term reliability MEMS device. This simple technique uses common semiconductor materials, techniques and equipment to provide a stable vacuum environment of less then 1 Pa in the sealed cavity. This environment protects the moving and/or particular component of the MEMS device against micro-contamination from the particles and slurry of the wafer dicing process, against fluctuations of the atmospheric conditions such as atmospheric pressure and relative humidity as to ensure a long-term reliability by keeping the moving and/or particular component.